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yosys/backends
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Clifford Wolf 9112850800
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark 
write_verilog: write RTLIL::Sa aka - as Verilog ?
2019-07-11 07:25:52 +02:00
..
aiger Rename __builtin_bswap32 -> bswap32 2019-07-09 09:35:09 -07:00
blif
btor Merge origin/master 2019-06-27 11:20:15 -07:00
edif
firrtl
ilang Allow attributes on individual switch cases in RTLIL. 2019-07-08 11:34:58 +00:00
intersynth
json Fix json formatting 2019-06-21 20:01:40 +02:00
protobuf Support filename rewrite in backends 2019-06-18 14:39:52 -07:00
simplec
smt2 Merge origin/master 2019-06-27 11:20:15 -07:00
smv
spice
table
verilog Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark 2019-07-11 07:25:52 +02:00