yosys/tests/verilog/func_tern_hint.ys at cff53d6d873493c2560a8ed1997a01f71c3571e6 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 20:38:44 +00:00

Zachary Snow a650d9079f verilog: fix width/sign detection for functions

2022-05-30 16:45:39 -04:00

5 lines

88 B

Plaintext

Raw Blame History

 read_verilog -sv func_tern_hint.sv
 proc
 opt
 sat -verify -seq 1 -prove-asserts -show-all