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6 lines
133 B
Verilog
6 lines
133 B
Verilog
module abc_bench_add8(
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input [7:0] a, b, c, d, e, f, g, h,
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output [7:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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