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https://github.com/YosysHQ/yosys
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259 lines
11 KiB
Text
259 lines
11 KiB
Text
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List of major changes and improvements between releases
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=======================================================
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Yosys 0.4 .. Yosys 0.4+
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-----------------------
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... TBD ...
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Yosys 0.3.0 .. Yosys 0.4
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------------------------
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* Platform Support
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- Added support for mxe-based cross-builds for win32
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- Added sourcecode-export as VisualStudio project
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- Added experimental EMCC (JavaScript) support
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* Verilog Frontend
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- Added -sv option for SystemVerilog (and automatic *.sv file support)
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- Added support for real-valued constants and constant expressions
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- Added support for non-standard "via_celltype" attribute on task/func
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- Added support for non-standard "module mod_name(...);" syntax
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- Added support for non-standard """ macro bodies
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- Added support for array with more than one dimension
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- Added support for $readmemh and $readmemb
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- Added support for DPI functions
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* Changes in internal cell library
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- Added $shift and $shiftx cell types
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- Added $alu, $lcu, $fa and $macc cell types
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- Removed $bu0 and $safe_pmux cell types
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- $mem/$memwr WR_EN input is now a per-data-bit enable signal
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- Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
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- Renamed ports of $lut cells (from I->O to A->Y)
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- Renamed $_INV_ to $_NOT_
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* Changes for simple synthesis flows
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- There is now a "synth" command with a recommended default script
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- Many improvements in synthesis of arithmetic functions to gates
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- Multiplieres and adders with many operands are using carry-save adder trees
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- Remaining adders are now implemented using Brent–Kung carry look-ahead adders
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- Various new high-level optimizations on RTL netlist
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- Various improvements in FSM optimization
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- Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
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* Changes in internal APIs and RTLIL
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- Added log_id() and log_cell() helper functions
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- Added function-like cell creation helpers
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- Added GetSize() function (like .size() but with int)
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- Major refactoring of RTLIL::Module and related classes
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- Major refactoring of RTLIL::SigSpec and related classes
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- Now RTLIL::IdString is essentially an int
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- Added macros for code coverage counters
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- Added some Makefile magic for pretty make logs
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- Added "kernel/yosys.h" with all the core definitions
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- Chanded a lot of code from FILE* to c++ streams
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- Added RTLIL::Monitor API and "trace" command
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- Added "Yosys" C++ namespace
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* Changes relevant to SAT solving
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- Added ezSAT::keep_cnf() and ezSAT::non_incremental()
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- Added native ezSAT support for vector shift ops
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- Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
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* New commands (or large improvements to commands)
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- Added "synth" command with default script
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- Added "share" (finally some real resource sharing)
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- Added "memory_share" (reduce number of ports on memories)
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- Added "wreduce" and "alumacc" commands
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- Added "opt -keepdc -fine -full -fast"
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- Added some "test_*" commands
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* Various other changes
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- Added %D and %c select operators
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- Added support for labels in yosys scripts
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- Added support for here-documents in yosys scripts
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- Support "+/" prefix for files from proc_share_dir
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- Added "autoidx" statement to ilang language
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- Switched from "yosys-svgviewer" to "xdot"
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- Renamed "stdcells.v" to "techmap.v"
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- Various bug fixes and small improvements
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- Improved welcome and bye messages
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Yosys 0.2.0 .. Yosys 0.3.0
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--------------------------
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* Driver program and overall behavior:
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- Added "design -push" and "design -pop"
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- Added "tee" command for redirecting log output
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* Changes in the internal cell library:
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- Added $dlatchsr and $_DLATCHSR_???_ cell types
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* Improvements in Verilog frontend:
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- Improved support for const functions (case, always, repeat)
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- The generate..endgenerate keywords are now optional
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- Added support for arrays of module instances
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- Added support for "`default_nettype" directive
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- Added support for "`line" directive
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* Other front- and back-ends:
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- Various changes to "write_blif" options
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- Various improvements in EDIF backend
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- Added "vhdl2verilog" pseudo-front-end
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- Added "verific" pseudo-front-end
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* Improvements in technology mapping:
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- Added support for recursive techmap
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- Added CONSTMSK and CONSTVAL features to techmap
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- Added _TECHMAP_CONNMAP_*_ feature to techmap
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- Added _TECHMAP_REPLACE_ feature to techmap
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- Added "connwrappers" command for wrap-extract-unwrap method
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- Added "extract -map %<design_name>" feature
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- Added "extract -ignore_param ..." and "extract -ignore_parameters"
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- Added "techmap -max_iter" option
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* Improvements to "eval" and "sat" framework:
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- Now include a copy of Minisat (with build fixes applied)
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- Switched to Minisat::SimpSolver as SAT back-end
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- Added "sat -dump_vcd" feature
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- Added "sat -dump_cnf" feature
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- Added "sat -initsteps <N>" feature
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- Added "freduce -stop <N>" feature
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- Added "fredure -dump <prefix>" feature
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* Integration with ABC:
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- Updated ABC rev to 7600ffb9340c
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* Improvements in the internal APIs:
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- Added RTLIL::Module::add... helper methods
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- Various build fixes for OSX (Darwin) and OpenBSD
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Yosys 0.1.0 .. Yosys 0.2.0
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--------------------------
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* Changes to the driver program:
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- Added "yosys -h" and "yosys -H"
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- Added support for backslash line continuation in scripts
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- Added support for #-comments in same line as command
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- Added "echo" and "log" commands
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* Improvements in Verilog frontend:
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- Added support for local registers in named blocks
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- Added support for "case" in "generate" blocks
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- Added support for $clog2 system function
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- Added support for basic SystemVerilog assert statements
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- Added preprocessor support for macro arguments
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- Added preprocessor support for `elsif statement
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- Added "verilog_defaults" command
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- Added read_verilog -icells option
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- Added support for constant sizes from parameters
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- Added "read_verilog -setattr"
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- Added support for function returning 'integer'
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- Added limited support for function calls in parameter values
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- Added "read_verilog -defer" to suppress evaluation of modules with default parameters
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* Other front- and back-ends:
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- Added BTOR backend
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- Added Liberty frontend
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* Improvements in technology mapping:
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- The "dfflibmap" command now strongly prefers solutions with
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no inverters in clock paths
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- The "dfflibmap" command now prefers cells with smaller area
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- Added support for multiple -map options to techmap
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- Added "dfflibmap" support for //-comments in liberty files
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- Added "memory_unpack" command to revert "memory_collect"
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- Added standard techmap rule "techmap -share_map pmux2mux.v"
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- Added "iopadmap -bits"
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- Added "setundef" command
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- Added "hilomap" command
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* Changes in the internal cell library:
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- Major rewrite of simlib.v for better compatibility with other tools
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- Added PRIORITY parameter to $memwr cells
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- Added TRANSPARENT parameter to $memrd cells
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- Added RD_TRANSPARENT parameter to $mem cells
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- Added $bu0 cell (always 0-extend, even undef MSB)
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- Added $assert cell type
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- Added $slice and $concat cell types
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* Integration with ABC:
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- Updated ABC to hg rev 2058c8ccea68
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- Tighter integration of ABC build with Yosys build. The make
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targets 'make abc' and 'make install-abc' are now obsolete.
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- Added support for passing FFs from one clock domain through ABC
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- Now always use BLIF as exchange format with ABC
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- Added support for "abc -script +<command_sequence>"
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- Improved standard ABC recipe
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- Added support for "keep" attribute to abc command
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- Added "abc -dff / -clk / -keepff" options
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* Improvements to "eval" and "sat" framework:
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- Added support for "0" and "~0" in right-hand side -set expressions
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- Added "eval -set-undef" and "eval -table"
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- Added "sat -set-init" and "sat -set-init-*" for sequential problems
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- Added undef support to SAT solver, incl. various new "sat" options
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- Added correct support for === and !== for "eval" and "sat"
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- Added "sat -tempinduct" (default -seq is now non-induction sequential)
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- Added "sat -prove-asserts"
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- Complete rewrite of the 'freduce' command
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- Added "miter" command
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- Added "sat -show-inputs" and "sat -show-outputs"
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- Added "sat -ignore_unknown_cells" (now produce an error by default)
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- Added "sat -falsify"
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- Now "sat -verify" and "sat -falsify" can also be used without "-prove"
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- Added "expose" command
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- Added support for @<sel_name> to sat and eval signal expressions
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* Changes in the 'make test' framework and auxilary test tools:
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- Added autotest.sh -p and -f options
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- Replaced autotest.sh ISIM support with XSIM support
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- Added test cases for SAT framework
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* Added "abbreviated IDs":
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- Now $<something>$foo can be abbriviated as $foo.
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- Usually this last part is a unique id (from RTLIL::autoidx)
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- This abbreviated IDs are now also used in "show" output
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* Other changes to selection framework:
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- Now */ is optional in */<mode>:<arg> expressions
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- Added "select -assert-none" and "select -assert-any"
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- Added support for matching modules by attribute (A:<expr>)
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- Added "select -none"
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- Added support for r:<expr> pattern for matching cell parameters
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- Added support for !=, <, <=, >=, > for attribute and parameter matching
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- Added support for %s for selecting sub-modules
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- Added support for %m for expanding selections to whole modules
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- Added support for i:*, o:* and x:* pattern for selecting module ports
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- Added support for s:<expr> pattern for matching wire width
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- Added support for %a operation to select wire aliases
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* Various other changes to commands and options:
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- The "ls" command now supports wildcards
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- Added "show -pause" and "show -format dot"
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- Added "show -color" support for cells
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- Added "show -label" and "show -notitle"
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- Added "dump -m" and "dump -n"
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- Added "history" command
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- Added "rename -hide"
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- Added "connect" command
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- Added "splitnets -driver"
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- Added "opt_const -mux_undef"
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- Added "opt_const -mux_bool"
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- Added "opt_const -undriven"
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- Added "opt -mux_undef -mux_bool -undriven -purge"
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- Added "hierarchy -libdir"
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- Added "hierarchy -purge_lib" (by default now do not remove lib cells)
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- Added "delete" command
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- Added "dump -append"
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- Added "setattr" and "setparam" commands
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- Added "design -stash/-copy-from/-copy-to"
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- Added "copy" command
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- Added "splice" command
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