mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-10 23:30:33 +00:00
5970be33fb
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion. Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops). To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion. Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
19 lines
366 B
Text
19 lines
366 B
Text
read_verilog -icells -specify <<EOT
|
|
(* abc9_box, blackbox *)
|
|
module box1(input i, output o);
|
|
specify
|
|
(i => o) = 1;
|
|
endspecify
|
|
endmodule
|
|
|
|
module top(input i, output o);
|
|
wire a, b, c, z;
|
|
$_AND_ a0(.A(b), .B(i), .Y(a));
|
|
$_AND_ b0(.A(a), .B(c), .Y(b));
|
|
$_AND_ c0(.A(b), .B(i), .Y(c));
|
|
box1 u_box(.i(i), .o(z));
|
|
assign o = c ^ z;
|
|
endmodule
|
|
EOT
|
|
|
|
abc9 -lut 4
|