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5970be33fb
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion. Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops). To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion. Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
16 lines
582 B
Text
16 lines
582 B
Text
read_verilog ../common/fsm.v
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hierarchy -top fsm
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proc
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flatten
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equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
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miter -equiv -make_assert -flatten gold gate miter
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sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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select -assert-count 4 t:SB_DFF
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select -assert-count 2 t:SB_DFFESR
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select -assert-max 16 t:SB_LUT4
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select -assert-none t:SB_DFFESR t:SB_DFF t:SB_LUT4 %% t:* %D
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