Eddie Hung f022645cd2 Fix bitwidth mismatch; suppresses iverilog warning		2019-12-11 13:02:07 -08:00
..
achronix
anlogic
common
coolrunner2
easic
ecp5	Fix bitwidth mismatch; suppresses iverilog warning	2019-12-11 13:02:07 -08:00
efinix
gowin	Use -match-init to not synth contradicting init values	2019-12-03 15:12:25 +01:00
greenpak4
ice40	ice40_opt to restore attributes/name when unwrapping	2019-12-09 14:29:29 -08:00
intel	synth_intel: a10gx -> arria10gx	2019-12-10 13:48:10 +00:00
sf2
xilinx	xilinx: Add tristate buffer mapping. (#1528)	2019-12-04 09:44:00 +01:00
.gitignore