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yosys/techlibs/common
Marcelina Kościelnicka 53ba3cf718 Fix the truth table for $_SR_* cells.
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
2020-04-15 17:17:48 +02:00
..
.gitignore
abc9_model.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v cmp2lcu: rename _90_lcu_cmp -> _80_lcu_cmp 2020-04-03 14:28:22 -07:00
cmp2lut.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
Makefile.inc
mul2dsp.v
pmux2mux.v
prep.cc
simcells.v Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
simlib.v Fix the truth table for $_SR_* cells. 2020-04-15 17:17:48 +02:00
synth.cc synth: only techmap cmp2{lut,lcu} if -lut 2020-04-03 14:28:22 -07:00
techmap.v