mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
6 lines
127 B
Verilog
6 lines
127 B
Verilog
module test(A, B, C, Y1, Y2);
|
|
input [7:0] A, B, C;
|
|
output [7:0] Y1 = A * B;
|
|
output [15:0] Y2 = A * C;
|
|
endmodule
|