mirror of
https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
16 lines
331 B
Plaintext
16 lines
331 B
Plaintext
read_verilog mymul_test.v
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hierarchy -check -top test
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techmap -map sym_mul_map.v \
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-map mymul_map.v;;
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rename test test_mapped
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read_verilog mymul_test.v
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miter -equiv test test_mapped miter
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flatten miter
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sat -verify -prove trigger 0 miter
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splitnets -ports test_mapped/A
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show -prefix mymul -format dot -notitle test_mapped
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