mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
16 lines
318 B
Verilog
16 lines
318 B
Verilog
module MYMUL(A, B, Y);
|
|
parameter WIDTH = 1;
|
|
input [WIDTH-1:0] A, B;
|
|
output reg [WIDTH-1:0] Y;
|
|
|
|
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
|
|
|
|
integer i;
|
|
always @* begin
|
|
Y = 0;
|
|
for (i = 0; i < WIDTH; i=i+1)
|
|
if (A[i])
|
|
Y = Y + (B << i);
|
|
end
|
|
endmodule
|