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15 lines
307 B
Verilog
15 lines
307 B
Verilog
module test(input clk, input [3:0] bar, output [3:0] foo);
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reg [3:0] foo = 0;
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reg [3:0] last_bar = 0;
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always @*
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foo[1:0] <= bar[1:0];
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always @(posedge clk)
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foo[3:2] <= bar[3:2];
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always @(posedge clk)
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last_bar <= bar;
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assert property (foo == {last_bar[3:2], bar[1:0]});
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endmodule
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