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abc9_model.v
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Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
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arith_map.v
|
analogdevices: update timing model
|
2025-10-06 23:56:44 +01:00 |
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brams.txt
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Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
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brams_defs.vh
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Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
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brams_map.v
|
Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
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cells_map.v
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Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
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cells_sim.v
|
analogdevices: Native LUTRAM primitives
|
2025-10-08 14:08:41 +13:00 |
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cells_xtra.py
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Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
|
cells_xtra.v
|
analogdevices: remove some extra cells!
|
2025-10-06 23:56:44 +01:00 |
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dsp_map.v
|
Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
|
ff_map.v
|
test suite
|
2025-10-06 23:56:44 +01:00 |
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lut_map.v
|
analogdevices: update timing model
|
2025-10-06 23:56:44 +01:00 |
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lutrams.txt
|
analogdevices: Native LUTRAM primitives
|
2025-10-08 14:08:41 +13:00 |
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lutrams_map.v
|
analogdevices: Native LUTRAM primitives
|
2025-10-08 14:08:41 +13:00 |
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Makefile.inc
|
Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
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mux_map.v
|
Create synth_analogdevices
|
2025-10-06 23:56:43 +01:00 |
|
retarget_map.v
|
analogdevices: user retargeting
|
2025-10-06 23:56:44 +01:00 |
