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Most of the word/coarse level cells have an assigned group and individual page. The gate/fine level cells are all on one page. Fix links to `cell_library.rst`.
124 lines
4.9 KiB
ReStructuredText
124 lines
4.9 KiB
ReStructuredText
.. role:: verilog(code)
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:language: Verilog
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Registers
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---------
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SR-type latches are represented by `$sr` cells. These cells have input ports
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``SET`` and ``CLR`` and an output port ``Q``. They have the following
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parameters:
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``WIDTH``
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The width of inputs ``SET`` and ``CLR`` and output ``Q``.
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``SET_POLARITY``
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The set input bits are active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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``CLR_POLARITY``
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The reset input bits are active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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Both set and reset inputs have separate bits for every output bit. When both the
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set and reset inputs of an `$sr` cell are active for a given bit index, the
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reset input takes precedence.
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D-type flip-flops are represented by `$dff` cells. These cells have a clock port
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``CLK``, an input port ``D`` and an output port ``Q``. The following parameters
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are available for `$dff` cells:
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``WIDTH``
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The width of input ``D`` and output ``Q``.
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``CLK_POLARITY``
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Clock is active on the positive edge if this parameter has the value ``1'b1``
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and on the negative edge if this parameter is ``1'b0``.
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D-type flip-flops with asynchronous reset are represented by `$adff` cells. As
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the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also
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have a single-bit ``ARST`` input port for the reset pin and the following
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additional two parameters:
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``ARST_POLARITY``
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The asynchronous reset is active-high if this parameter has the value
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``1'b1`` and active-low if this parameter is ``1'b0``.
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``ARST_VALUE``
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The state of ``Q`` will be set to this value when the reset is active.
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Usually these cells are generated by the `proc` pass using the information in
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the designs RTLIL::Process objects.
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D-type flip-flops with synchronous reset are represented by `$sdff` cells. As
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the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also
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have a single-bit ``SRST`` input port for the reset pin and the following
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additional two parameters:
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``SRST_POLARITY``
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The synchronous reset is active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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``SRST_VALUE``
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The state of ``Q`` will be set to this value when the reset is active.
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Note that the `$adff` and `$sdff` cells can only be used when the reset value is
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constant.
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D-type flip-flops with asynchronous load are represented by `$aldff` cells. As
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the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition they also
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have a single-bit ``ALOAD`` input port for the async load enable pin, a ``AD``
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input port with the same width as data for the async load data, and the
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following additional parameter:
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``ALOAD_POLARITY``
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The asynchronous load is active-high if this parameter has the value ``1'b1``
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and active-low if this parameter is ``1'b0``.
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D-type flip-flops with asynchronous set and reset are represented by `$dffsr`
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cells. As the `$dff` cells they have ``CLK``, ``D`` and ``Q`` ports. In addition
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they also have multi-bit ``SET`` and ``CLR`` input ports and the corresponding
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polarity parameters, like `$sr` cells.
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D-type flip-flops with enable are represented by `$dffe`, `$adffe`, `$aldffe`,
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`$dffsre`, `$sdffe`, and `$sdffce` cells, which are enhanced variants of `$dff`,
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`$adff`, `$aldff`, `$dffsr`, `$sdff` (with reset over enable) and `$sdff` (with
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enable over reset) cells, respectively. They have the same ports and parameters
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as their base cell. In addition they also have a single-bit ``EN`` input port
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for the enable pin and the following parameter:
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``EN_POLARITY``
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The enable input is active-high if this parameter has the value ``1'b1`` and
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active-low if this parameter is ``1'b0``.
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D-type latches are represented by `$dlatch` cells. These cells have an enable
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port ``EN``, an input port ``D``, and an output port ``Q``. The following
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parameters are available for `$dlatch` cells:
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``WIDTH``
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The width of input ``D`` and output ``Q``.
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``EN_POLARITY``
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The enable input is active-high if this parameter has the value ``1'b1`` and
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active-low if this parameter is ``1'b0``.
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The latch is transparent when the ``EN`` input is active.
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D-type latches with reset are represented by `$adlatch` cells. In addition to
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`$dlatch` ports and parameters, they also have a single-bit ``ARST`` input port
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for the reset pin and the following additional parameters:
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``ARST_POLARITY``
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The asynchronous reset is active-high if this parameter has the value
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``1'b1`` and active-low if this parameter is ``1'b0``.
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``ARST_VALUE``
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The state of ``Q`` will be set to this value when the reset is active.
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D-type latches with set and reset are represented by `$dlatchsr` cells. In
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addition to `$dlatch` ports and parameters, they also have multi-bit ``SET`` and
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``CLR`` input ports and the corresponding polarity parameters, like `$sr` cells.
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.. autocellgroup:: reg
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:members:
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:source:
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:linenos:
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