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https://github.com/YosysHQ/yosys
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62 lines
1.9 KiB
C++
62 lines
1.9 KiB
C++
#include <gtest/gtest.h>
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#include "kernel/rtlil.h"
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#include "kernel/yosys.h"
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#include "tests/unit/yosysSetupEnv.h"
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YOSYS_NAMESPACE_BEGIN
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namespace RTLIL {
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TEST(RtlilStrTest, DesignToString) {
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Design design;
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Module *mod = design.addModule(design.twines.add(std::string{"\\my_module"}));
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mod->addWire(design.twines.add(std::string{"\\my_wire"}), 1);
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std::string design_str = design.to_rtlil_str();
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EXPECT_NE(design_str.find("module \\my_module"), std::string::npos);
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EXPECT_NE(design_str.find("end"), std::string::npos);
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}
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TEST(RtlilStrTest, ModuleToString) {
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Design design;
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Module *mod = design.addModule(design.twines.add(std::string{"\\test_mod"}));
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Wire *wire = mod->addWire(design.twines.add(std::string{"\\clk"}), 1);
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wire->port_input = true;
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std::string mod_str = mod->to_rtlil_str();
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EXPECT_NE(mod_str.find("module \\test_mod"), std::string::npos);
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EXPECT_NE(mod_str.find("wire"), std::string::npos);
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EXPECT_NE(mod_str.find("\\clk"), std::string::npos);
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EXPECT_NE(mod_str.find("input"), std::string::npos);
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}
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TEST(RtlilStrTest, WireToString) {
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Design design;
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Module *mod = design.addModule(design.twines.add(std::string{"\\m"}));
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Wire *wire = mod->addWire(design.twines.add(std::string{"\\data"}), 8);
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std::string wire_str = wire->to_rtlil_str();
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EXPECT_NE(wire_str.find("wire"), std::string::npos);
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EXPECT_NE(wire_str.find("width 8"), std::string::npos);
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EXPECT_NE(wire_str.find("\\data"), std::string::npos);
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}
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TEST(RtlilStrTest, CellToString) {
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Design design;
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Module *mod = design.addModule(design.twines.add(std::string{"\\m"}));
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Cell *cell = mod->addCell(design.twines.add(std::string{"\\u1"}), design.twines.add(std::string{"\\my_cell_type"}));
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std::string cell_str = cell->to_rtlil_str();
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EXPECT_NE(cell_str.find("cell"), std::string::npos);
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EXPECT_NE(cell_str.find("\\my_cell_type"), std::string::npos);
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EXPECT_NE(cell_str.find("\\u1"), std::string::npos);
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}
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}
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YOSYS_NAMESPACE_END
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