mirror of
https://github.com/YosysHQ/yosys
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102 lines
3.3 KiB
C++
102 lines
3.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/qcsat.h"
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USING_YOSYS_NAMESPACE
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std::vector<int> QuickConeSat::importSig(SigSpec sig)
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{
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sig = modwalker.sigmap(sig);
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for (auto bit : sig)
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bits_queue.insert(bit);
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return satgen.importSigSpec(sig);
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}
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int QuickConeSat::importSigBit(SigBit bit)
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{
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bit = modwalker.sigmap(bit);
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bits_queue.insert(bit);
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return satgen.importSigBit(bit);
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}
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void QuickConeSat::prepare()
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{
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while (!bits_queue.empty())
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{
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, bits_queue);
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for (auto bit : bits_queue)
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if (bit.wire && bit.wire->get_bool_attribute(ID::onehot) && !imported_onehot.count(bit.wire))
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{
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std::vector<int> bits = satgen.importSigSpec(bit.wire);
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for (int i : bits)
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for (int j : bits)
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if (i != j)
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ez->assume(ez->NOT(i), j);
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imported_onehot.insert(bit.wire);
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}
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bits_queue.clear();
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for (auto &pbit : portbits)
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{
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if (imported_cells.count(pbit.cell))
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continue;
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if (cell_complexity(pbit.cell) > max_cell_complexity)
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continue;
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if (max_cell_outs && GetSize(modwalker.cell_outputs[pbit.cell]) > max_cell_outs)
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continue;
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auto &inputs = modwalker.cell_inputs[pbit.cell];
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bits_queue.insert(inputs.begin(), inputs.end());
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satgen.importCell(pbit.cell);
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imported_cells.insert(pbit.cell);
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}
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if (max_cell_count && GetSize(imported_cells) > max_cell_count)
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break;
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}
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}
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int QuickConeSat::cell_complexity(RTLIL::Cell *cell)
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{
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if (cell->type.in(TW($concat), TW($slice), TW($pos), TW($buf), TW($_BUF_)))
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return 0;
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if (cell->type.in(TW($not), TW($and), TW($or), TW($xor), TW($xnor),
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TW($reduce_and), TW($reduce_or), TW($reduce_xor),
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TW($reduce_xnor), TW($reduce_bool),
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TW($logic_not), TW($logic_and), TW($logic_or),
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TW($eq), TW($ne), TW($eqx), TW($nex), TW($fa),
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TW($mux), TW($pmux), TW($bmux), TW($demux), TW($lut), TW($sop),
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TW($_NOT_), TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_),
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TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_),
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TW($_MUX_), TW($_NMUX_), TW($_MUX4_), TW($_MUX8_), TW($_MUX16_),
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TW($_AOI3_), TW($_OAI3_), TW($_AOI4_), TW($_OAI4_)))
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return 1;
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if (cell->type.in(TW($neg), TW($add), TW($sub), TW($alu), TW($lcu),
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TW($lt), TW($le), TW($gt), TW($ge)))
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return 2;
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if (cell->type.in(TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)))
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return 3;
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if (cell->type.in(TW($mul), TW($macc), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($pow)))
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return 4;
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// Unknown cell.
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return 5;
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}
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