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yosys/tests/sat/asserts_seq.ys
Clifford Wolf 482d9208aa Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
2014-06-12 11:54:20 +02:00

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read_verilog -sv asserts_seq.v
hierarchy; proc; opt
sat -verify -prove-asserts -tempinduct -seq 1 test_001
sat -falsify -prove-asserts -tempinduct -seq 1 test_002
sat -falsify -prove-asserts -tempinduct -seq 1 test_003
sat -falsify -prove-asserts -tempinduct -seq 1 test_004
sat -verify -prove-asserts -tempinduct -seq 1 test_005
sat -verify -prove-asserts -seq 2 test_001
sat -falsify -prove-asserts -seq 2 test_002
sat -falsify -prove-asserts -seq 2 test_003
sat -falsify -prove-asserts -seq 2 test_004
sat -verify -prove-asserts -seq 2 test_005