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yosys/techlibs/quicklogic
History
Catherine cad5353a2a Migrate build system to CMake 
See #5895 for details.

This commit does not include CI or documentation changes.
2026-05-21 23:50:04 +00:00
..
common synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
pp3 synth_quicklogic: rearrange files to prepare for adding more architectures 2023-12-04 15:52:02 +01:00
qlf_k6n10f Drop timestamp in generate_bram_types_sim.py 2024-10-30 08:47:18 +01:00
CMakeLists.txt Migrate build system to CMake 2026-05-21 23:50:04 +00:00
ql_bram_merge.cc Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
ql_bram_types.cc Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
ql_dsp_io_regs.cc Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
ql_dsp_macc.cc Fixing couple more conversion errors 2026-05-14 15:58:58 +02:00
ql_dsp_macc.pmg ql_dsp_macc: Tune DSP inference code 2023-12-04 15:52:02 +01:00
ql_dsp_simd.cc Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
ql_ioff.cc Remove .c_str() from parameters to log_debug() 2025-09-23 19:10:33 +12:00
synth_quicklogic.cc Add check before flatten in synth_*. 2026-05-05 14:06:58 +02:00