Clifford Wolf bdc316db50 Added $anyseq cell type		2016-10-14 15:24:03 +02:00
..
APPNOTE_011_Design_Investigation
CHAPTER_Eval
CHAPTER_Prog	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
CHAPTER_StateOfTheArt
PRESENTATION_ExAdv
PRESENTATION_ExOth
PRESENTATION_ExSyn
PRESENTATION_Intro
PRESENTATION_Prog	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
.gitignore
APPNOTE_010_Verilog_to_BLIF.tex
APPNOTE_011_Design_Investigation.tex
APPNOTE_012_Verilog_to_BTOR.tex	Renamed opt_const to opt_expr	2016-03-31 08:46:56 +02:00
appnotes.sh
CHAPTER_Appnotes.tex	Updated command reference in manual	2016-02-14 11:02:11 +01:00
CHAPTER_Approach.tex
CHAPTER_Auxlibs.tex
CHAPTER_Auxprogs.tex
CHAPTER_Basics.tex
CHAPTER_CellLib.tex	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
CHAPTER_Eval.tex
CHAPTER_Intro.tex
CHAPTER_Optimize.tex	Added warning about adding fsm_encoding attributes to wires to manual	2016-07-08 18:31:31 +02:00
CHAPTER_Overview.tex	Renamed opt_share to opt_merge	2016-03-31 08:52:49 +02:00
CHAPTER_Prog.tex
CHAPTER_StateOfTheArt.tex
CHAPTER_Techmap.tex
CHAPTER_Verilog.tex
clean.sh
command-reference-manual.tex	user-facing spelling fixes	2016-02-28 15:14:01 -07:00
literature.bib
manual.sh
manual.tex	Fix a few typos in the manual	2016-04-03 14:29:11 +02:00
presentation.sh
presentation.tex
PRESENTATION_ExAdv.tex
PRESENTATION_ExOth.tex
PRESENTATION_ExSyn.tex	Renamed opt_share to opt_merge	2016-03-31 08:52:49 +02:00
PRESENTATION_Intro.tex
PRESENTATION_Prog.tex	Minor presentation fixes	2016-05-14 11:35:39 +02:00
weblinks.bib