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yosys/techlibs/ice40
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Clifford Wolf e66e8fb59d
Merge pull request #1184 from whitequark/synth-better-labels 
synth_{ice40,ecp5}: more sensible pass label naming
2019-07-18 15:34:28 +02:00
..
tests
.gitignore
abc_hx.box $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
abc_hx.lut
abc_lp.box $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
abc_lp.lut
abc_u.box $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
abc_u.lut
arith_map.v $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
brams.txt
brams_init.py
brams_map.v
cells_map.v $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
cells_sim.v $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
ice40_unlut.cc ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map 2019-07-16 23:57:15 +02:00
latches_map.v
Makefile.inc Also update Makefile.inc 2019-04-18 09:58:34 -07:00
synth_ice40.cc Merge pull request #1184 from whitequark/synth-better-labels 2019-07-18 15:34:28 +02:00