Gary Wong ca7d94af99 verilog: improve string literal matching speed (fixes #5076) ... Use a greedy regular expression to match input inside a string literal, so that flex can accumulate a longer match instead of invoking a rule for each individual character.		2025-05-31 22:38:44 -06:00
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.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
const2ast.cc	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
Makefile.inc	Treat all bison warnings as errors in verilog front-end	2020-07-15 11:57:31 +02:00
preproc.cc	set default_nettype to wire for resetall	2022-08-10 13:28:19 +02:00
preproc.h	verilog: save and restore overwritten macro arguments	2021-07-28 21:52:16 -04:00
verilog_frontend.cc	read_verilog_file_list: change short help message to start with lower case	2025-04-08 13:20:16 +02:00
verilog_frontend.h	verilog: Squash a memory leak.	2021-06-14 17:07:41 +02:00
verilog_lexer.l	verilog: improve string literal matching speed (fixes #5076)	2025-05-31 22:38:44 -06:00
verilog_parser.y	Merge pull request #5143 from YosysHQ/krys/typedef_struct_global	2025-05-31 09:59:26 +12:00