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10 lines
180 B
Verilog
10 lines
180 B
Verilog
// Tristate Description Using Concurrent Assignment
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// File: tristates_2.v
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//
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module tristates_2 (T, I, O);
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input T, I;
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output O;
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assign O = (~T) ? I: 1'bZ;
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endmodule
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