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17 lines
243 B
Verilog
17 lines
243 B
Verilog
// Tristate Description Using Combinatorial Always Block
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// File: tristates_1.v
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//
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module tristates_1 (T, I, O);
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input T, I;
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output O;
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reg O;
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always @(T or I)
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begin
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if (~T)
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O = I;
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else
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O = 1'bZ;
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end
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endmodule
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