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18 lines
344 B
Verilog
18 lines
344 B
Verilog
// Multiplexer using case statement
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module mux4 (sel, a, b, c, d, outmux);
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input [1:0] sel;
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input [1:0] a, b, c, d;
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output [1:0] outmux;
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reg [1:0] outmux;
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always @ *
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begin
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case(sel)
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2'b00 : outmux = a;
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2'b01 : outmux = b;
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2'b10 : outmux = c;
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2'b11 : outmux = d;
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endcase
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end
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endmodule
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