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42 lines
986 B
Verilog
42 lines
986 B
Verilog
// Squarer support for DSP block (DSP48E2) with
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// pre-adder configured
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// as subtractor
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// File: squarediffmult.v
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module squarediffmult # (parameter SIZEIN = 16)
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(
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input clk, ce, rst,
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input signed [SIZEIN-1:0] a, b,
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output signed [2*SIZEIN+1:0] square_out
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);
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// Declare registers for intermediate values
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reg signed [SIZEIN-1:0] a_reg, b_reg;
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reg signed [SIZEIN:0] diff_reg;
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reg signed [2*SIZEIN+1:0] m_reg, p_reg;
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always @(posedge clk)
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begin
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if (rst)
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begin
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a_reg <= 0;
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b_reg <= 0;
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diff_reg <= 0;
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m_reg <= 0;
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p_reg <= 0;
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end
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else
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if (ce)
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begin
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a_reg <= a;
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b_reg <= b;
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diff_reg <= a_reg - b_reg;
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m_reg <= diff_reg * diff_reg;
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p_reg <= m_reg;
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end
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end
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// Output result
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assign square_out = p_reg;
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endmodule // squarediffmult
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