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52 lines
1.7 KiB
Verilog
52 lines
1.7 KiB
Verilog
// This module performs subtraction of two inputs, squaring on the diff
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// and then accumulation
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// This can be implemented in 1 DSP Block (Ultrascale architecture)
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// File : squarediffmacc.v
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module squarediffmacc # (
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//Default parameters were changed because of slow test
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//parameter SIZEIN = 16,
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//SIZEOUT = 40
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parameter SIZEIN = 8,
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SIZEOUT = 20
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)
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(
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input clk,
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input ce,
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input sload,
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input signed [SIZEIN-1:0] a,
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input signed [SIZEIN-1:0] b,
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output signed [SIZEOUT+1:0] accum_out
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);
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// Declare registers for intermediate values
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reg signed [SIZEIN-1:0] a_reg, b_reg;
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reg signed [SIZEIN:0] diff_reg;
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reg sload_reg;
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reg signed [2*SIZEIN+1:0] m_reg;
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reg signed [SIZEOUT-1:0] adder_out, old_result;
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always @(sload_reg or adder_out)
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if (sload_reg)
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old_result <= 0;
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else
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// 'sload' is now and opens the accumulation loop.
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// The accumulator takes the next multiplier output
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// in the same cycle.
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old_result <= adder_out;
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always @(posedge clk)
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if (ce)
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begin
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a_reg <= a;
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b_reg <= b;
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diff_reg <= a_reg - b_reg;
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m_reg <= diff_reg * diff_reg;
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sload_reg <= sload;
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// Store accumulation result into a register
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adder_out <= old_result + m_reg;
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end
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// Output accumulation result
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assign accum_out = adder_out;
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endmodule // squarediffmacc
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