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16 lines
549 B
Text
16 lines
549 B
Text
read_verilog sfir_shifter.v
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hierarchy -top sfir_shifter
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proc
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flatten
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#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'.
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#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd sfir_shifter
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#Vivado synthesizes 32 FDRE, 16 SRL16E.
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stat
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select -assert-count 1 t:BUFG
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select -assert-count 16 t:SRL16E
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select -assert-none t:BUFG t:SRL16E %% t:* %D
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