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19 lines
494 B
Verilog
19 lines
494 B
Verilog
//sfir_shifter.v
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(* dont_touch = "yes" *)
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module sfir_shifter #(parameter dsize = 16, nbtap = 4)
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(input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout);
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(* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
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integer i;
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always @(posedge clk)
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begin
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tmp[0] <= datain;
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for (i=0; i<=2*nbtap-2; i=i+1)
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tmp[i+1] <= tmp[i];
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end
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assign dataout = tmp[2*nbtap-1];
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endmodule
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// sfir_shifter
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