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29 lines
533 B
Verilog
29 lines
533 B
Verilog
// Block RAM with Resettable Data Output
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// File: rams_sp_rf_rst.v
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module rams_sp_rf_rst (clk, en, we, rst, addr, di, dout);
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input clk;
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input en;
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input we;
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input rst;
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input [9:0] addr;
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input [15:0] di;
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output [15:0] dout;
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reg [15:0] ram [1023:0];
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reg [15:0] dout;
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always @(posedge clk)
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begin
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if (en) //optional enable
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begin
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if (we) //write enable
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ram[addr] <= di;
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if (rst) //optional reset
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dout <= 0;
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else
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dout <= ram[addr];
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end
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end
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endmodule
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