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26 lines
401 B
Verilog
26 lines
401 B
Verilog
// Single-Port Block RAM Read-First Mode
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// rams_sp_rf.v
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module rams_sp_rf (clk, en, we, addr, di, dout);
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input clk;
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input we;
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input en;
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input [9:0] addr;
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input [15:0] di;
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output [15:0] dout;
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reg [15:0] RAM [1023:0];
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reg [15:0] dout;
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always @(posedge clk)
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begin
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if (en)
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begin
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if (we)
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RAM[addr]<=di;
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dout <= RAM[addr];
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end
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end
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endmodule
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