mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-29 14:30:08 +00:00
26 lines
408 B
Verilog
26 lines
408 B
Verilog
// Single-Port Block RAM No-Change Mode
|
|
// File: rams_sp_nc.v
|
|
|
|
module rams_sp_nc (clk, we, en, addr, di, dout);
|
|
|
|
input clk;
|
|
input we;
|
|
input en;
|
|
input [9:0] addr;
|
|
input [15:0] di;
|
|
output [15:0] dout;
|
|
|
|
reg [15:0] RAM [1023:0];
|
|
reg [15:0] dout;
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (en)
|
|
begin
|
|
if (we)
|
|
RAM[addr] <= di;
|
|
else
|
|
dout <= RAM[addr];
|
|
end
|
|
end
|
|
endmodule
|