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42 lines
742 B
Verilog
42 lines
742 B
Verilog
// Block RAM with Optional Output Registers
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// File: rams_pipeline
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module rams_pipeline (clk1, clk2, we, en1, en2, addr1, addr2, di, res1, res2);
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input clk1;
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input clk2;
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input we, en1, en2;
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input [9:0] addr1;
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input [9:0] addr2;
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input [15:0] di;
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output [15:0] res1;
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output [15:0] res2;
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reg [15:0] res1;
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reg [15:0] res2;
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reg [15:0] RAM [1023:0];
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reg [15:0] do1;
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reg [15:0] do2;
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always @(posedge clk1)
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begin
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if (we == 1'b1)
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RAM[addr1] <= di;
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do1 <= RAM[addr1];
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end
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always @(posedge clk2)
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begin
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do2 <= RAM[addr2];
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end
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always @(posedge clk1)
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begin
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if (en1 == 1'b1)
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res1 <= do1;
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end
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always @(posedge clk2)
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begin
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if (en2 == 1'b1)
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res2 <= do2;
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end
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endmodule
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