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24 lines
439 B
Verilog
24 lines
439 B
Verilog
// Initializing Block RAM from external data file
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// Binary data
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// File: rams_init_file.v
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module rams_init_file (clk, we, addr, din, dout);
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input clk;
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input we;
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input [5:0] addr;
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input [31:0] din;
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output [31:0] dout;
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reg [31:0] ram [0:63];
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reg [31:0] dout;
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initial begin
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$readmemb("rams_init_file.data",ram);
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end
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always @(posedge clk)
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begin
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if (we)
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ram[addr] <= din;
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dout <= ram[addr];
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end endmodule
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