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24 lines
406 B
Verilog
24 lines
406 B
Verilog
// Dual-Port RAM with Asynchronous Read (Distributed RAM)
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// File: rams_dist.v
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module rams_dist (clk, we, a, dpra, di, spo, dpo);
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input clk;
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input we;
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input [5:0] a;
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input [5:0] dpra;
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input [15:0] di;
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output [15:0] spo;
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output [15:0] dpo;
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reg [15:0] ram [63:0];
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always @(posedge clk)
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begin
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if (we)
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ram[a] <= di;
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end
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assign spo = ram[a];
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assign dpo = ram[dpra];
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endmodule
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