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30 lines
526 B
Verilog
30 lines
526 B
Verilog
// Simple Dual-Port Block RAM with Two Clocks
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// File: simple_dual_two_clocks.v
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module simple_dual_two_clocks (clka,clkb,ena,enb,wea,addra,addrb,dia,dob);
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input clka,clkb,ena,enb,wea;
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input [9:0] addra,addrb;
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input [15:0] dia;
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output [15:0] dob;
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reg [15:0] ram [1023:0];
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reg [15:0] dob;
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always @(posedge clka)
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begin
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if (ena)
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begin
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if (wea)
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ram[addra] <= dia;
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end
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end
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always @(posedge clkb)
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begin
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if (enb)
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begin
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dob <= ram[addrb];
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end
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end
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endmodule
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