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25 lines
No EOL
475 B
Verilog
25 lines
No EOL
475 B
Verilog
// Simple Dual-Port Block RAM with One Clock
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// File: simple_dual_one_clock.v
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module simple_dual_one_clock (clk,ena,enb,wea,addra,addrb,dia,dob);
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input clk,ena,enb,wea;
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input [9:0] addra,addrb;
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input [15:0] dia;
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output [15:0] dob;
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reg [15:0] ram [1023:0];
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reg [15:0] doa,dob;
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always @(posedge clk) begin
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if (ena) begin
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if (wea)
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ram[addra] <= dia;
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end
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end
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always @(posedge clk) begin
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if (enb)
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dob <= ram[addrb];
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end
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endmodule |