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23 lines
763 B
Text
23 lines
763 B
Text
read_verilog presubmult.v
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hierarchy -top presubmult
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proc
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flatten
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd presubmult
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#Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8)
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stat
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select -assert-count 1 t:BUFG
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select -assert-count 51 t:FDRE
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select -assert-count 75 t:LUT2
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select -assert-count 10 t:LUT3
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select -assert-count 24 t:LUT4
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select -assert-count 15 t:LUT5
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select -assert-count 136 t:LUT6
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select -assert-count 24 t:MUXCY
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select -assert-count 46 t:MUXF7
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select -assert-count 14 t:MUXF8
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select -assert-count 26 t:XORCY
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select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
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