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43 lines
1.1 KiB
Verilog
43 lines
1.1 KiB
Verilog
//
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// Pre-adder support in subtract mode for DSP block
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// File: presubmult.v
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module presubmult # (//Default parameters were changed because of slow test
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// parameter SIZEIN = 16
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parameter SIZEIN = 8
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)
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(
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input clk, ce, rst,
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input signed [SIZEIN-1:0] a, b, c,
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output signed [2*SIZEIN:0] presubmult_out
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);
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// Declare registers for intermediate values
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reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
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reg signed [SIZEIN:0] add_reg;
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reg signed [2*SIZEIN:0] m_reg, p_reg;
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always @(posedge clk)
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if (rst)
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begin
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a_reg <= 0;
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b_reg <= 0;
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c_reg <= 0;
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add_reg <= 0;
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m_reg <= 0;
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p_reg <= 0;
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end
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else if (ce)
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begin
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a_reg <= a;
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b_reg <= b;
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c_reg <= c;
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add_reg <= a - b;
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m_reg <= add_reg * c_reg;
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p_reg <= m_reg;
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end
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// Output accumulation result
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assign presubmult_out = p_reg;
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endmodule // presubmult
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