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33 lines
688 B
Verilog
33 lines
688 B
Verilog
// Unsigned 16x24-bit Multiplier
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// 1 latency stage on operands
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// 3 latency stage after the multiplication
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// File: multipliers2.v
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//
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module mult_unsigned (clk, A, B, RES);
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//Default parameters were changed because of slow test
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//parameter WIDTHA = 16;
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//parameter WIDTHB = 24;
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parameter WIDTHA = 8;
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parameter WIDTHB = 12;
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input clk;
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input [WIDTHA-1:0] A;
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input [WIDTHB-1:0] B;
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output [WIDTHA+WIDTHB-1:0] RES;
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reg [WIDTHA-1:0] rA;
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reg [WIDTHB-1:0] rB;
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reg [WIDTHA+WIDTHB-1:0] M [3:0];
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integer i;
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always @(posedge clk)
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begin
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rA <= A;
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rB <= B;
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M[0] <= rA * rB;
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for (i = 0; i < 3; i = i+1)
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M[i+1] <= M[i];
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end
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assign RES = M[3];
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endmodule
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