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47 lines
1.3 KiB
Verilog
47 lines
1.3 KiB
Verilog
// Signed 40-bit streaming accumulator with 16-bit inputs
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// File: macc.v
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//
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module macc # (
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//Default parameters were changed because of slow test
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// parameter SIZEIN = 16, SIZEOUT = 40
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// parameter SIZEIN = 12, SIZEOUT = 30
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parameter SIZEIN = 8, SIZEOUT = 20
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)
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(
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input clk, ce, sload,
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input signed [SIZEIN-1:0] a, b,
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output signed [SIZEOUT-1:0] accum_out
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);
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// Declare registers for intermediate values
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reg signed [SIZEIN-1:0] a_reg, b_reg;
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reg sload_reg;
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reg signed [2*SIZEIN:0] mult_reg;
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reg signed [SIZEOUT-1:0] adder_out, old_result;
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always @(adder_out or sload_reg)
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begin
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if (sload_reg)
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old_result <= 0;
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else
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// 'sload' is now active (=low) and opens the accumulation loop.
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// The accumulator takes the next multiplier output in
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// the same cycle.
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old_result <= adder_out;
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end
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always @(posedge clk)
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if (ce)
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begin
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a_reg <= a;
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b_reg <= b;
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mult_reg <= a_reg * b_reg;
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sload_reg <= sload;
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// Store accumulation result into a register
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adder_out <= old_result + mult_reg;
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end
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// Output accumulation result
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assign accum_out = adder_out;
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endmodule // macc
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