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17 lines
297 B
Verilog
17 lines
297 B
Verilog
// Latch with Positive Gate and Asynchronous Reset
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// File: latches.v
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module latches (
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input G,
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input D,
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input CLR,
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output reg Q
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);
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always @ *
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begin
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if(CLR)
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Q = 0;
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else if(G)
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Q = D;
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end
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endmodule
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