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42 lines
914 B
Verilog
42 lines
914 B
Verilog
// State Machine with single sequential block
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//fsm_1.v
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module fsm_1(clk,reset,flag,sm_out);
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input clk,reset,flag;
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output reg sm_out;
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parameter s1 = 3'b000;
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parameter s2 = 3'b001;
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parameter s3 = 3'b010;
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parameter s4 = 3'b011;
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parameter s5 = 3'b111;
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reg [2:0] state;
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always@(posedge clk)
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begin
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if(reset)
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begin
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state <= s1;
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sm_out <= 1'b1;
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end
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else
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begin
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case(state)
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s1: if(flag)
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begin
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state <= s2;
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sm_out <= 1'b1;
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end
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else
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begin
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state <= s3;
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sm_out <= 1'b0;
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end
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s2: begin state <= s4; sm_out <= 1'b0; end
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s3: begin state <= s4; sm_out <= 1'b0; end
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s4: begin state <= s5; sm_out <= 1'b1; end
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s5: begin state <= s1; sm_out <= 1'b1; end
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endcase
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end
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end
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endmodule
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