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42 lines
906 B
Verilog
42 lines
906 B
Verilog
// Single-Port BRAM with Byte-wide Write Enable
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// Read-First mode
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// Single-process description
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// Compact description of the write with a generate-for
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// statement
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// Column width and number of columns easily configurable
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//
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// bytewrite_ram_1b.v
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//
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module bytewrite_ram_1b (clk, we, addr, di, do);
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parameter SIZE = 1024;
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parameter ADDR_WIDTH = 10;
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parameter COL_WIDTH = 8;
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parameter NB_COL = 4;
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input clk;
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input [NB_COL-1:0] we;
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input [ADDR_WIDTH-1:0] addr;
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input [NB_COL*COL_WIDTH-1:0] di;
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output reg [NB_COL*COL_WIDTH-1:0] do;
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reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
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always @(posedge clk)
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begin
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do <= RAM[addr];
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end
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generate genvar i;
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for (i = 0; i < NB_COL; i = i+1)
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begin
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always @(posedge clk)
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begin
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if (we[i])
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RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
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end
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end
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endgenerate
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endmodule
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