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15 lines
546 B
Text
15 lines
546 B
Text
read_verilog black_box_1.v
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hierarchy -top black_box_1
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proc
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tribuf
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flatten
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synth
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#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd black_box_1 # Constrain all select calls below inside the top module
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#Vivado synthesizes 1 black box.
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#stat
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#select -assert-count 0 t:LUT1
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#select -assert-count 1 t:$_TBUF_
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#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
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