mirror of
https://github.com/YosysHQ/yosys
synced 2025-08-29 14:30:08 +00:00
29 lines
828 B
Text
29 lines
828 B
Text
read_verilog asym_ram_tdp_write_first.v
|
|
hierarchy -top asym_ram_tdp_write_first
|
|
proc
|
|
memory -nomap
|
|
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
|
memory
|
|
opt -full
|
|
|
|
# TODO
|
|
#equiv_opt -run prove: -assert null
|
|
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
|
|
|
|
design -load postopt
|
|
cd asym_ram_tdp_write_first
|
|
stat
|
|
#Vivado synthesizes 1 RAMB18E1.
|
|
select -assert-count 2 t:BUFG
|
|
select -assert-count 200 t:FDRE
|
|
select -assert-count 10 t:LUT2
|
|
select -assert-count 44 t:LUT3
|
|
select -assert-count 81 t:LUT4
|
|
select -assert-count 104 t:LUT5
|
|
select -assert-count 560 t:LUT6
|
|
select -assert-count 261 t:MUXF7
|
|
select -assert-count 127 t:MUXF8
|
|
|
|
|
|
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
|