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31 lines
931 B
Text
31 lines
931 B
Text
read_verilog asym_ram_sdp_write_wider.v
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hierarchy -top asym_ram_sdp_write_wider
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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# TODO
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#equiv_opt -run prove: -assert null
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
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design -load postopt
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cd asym_ram_sdp_write_wider
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stat
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#Vivado synthesizes 1 RAMB18E1.
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select -assert-count 2 t:BUFG
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select -assert-count 1028 t:FDRE
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select -assert-count 170 t:LUT2
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select -assert-count 6 t:LUT3
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select -assert-count 518 t:LUT4
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select -assert-count 10 t:LUT5
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select -assert-count 484 t:LUT6
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select -assert-count 157 t:MUXF7
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select -assert-count 3 t:MUXF8
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#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4
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#select -assert-count 8 t:RAM128X1D
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select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
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