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Code Activity
yosys/passes
History
Emil J. Tywoniak ca632e82c4 rtlil: set Module* on inner-process AttrObjects at construction
2026-06-10 14:54:12 +02:00
..
cmds rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
equiv WIP 2026-06-10 14:52:50 +02:00
fsm WIP 2026-06-10 14:52:50 +02:00
hierarchy twine 2026-06-10 14:53:45 +02:00
memory rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
opt twine 2026-06-10 14:53:45 +02:00
pmgen pmgen: hold sigmap pointer instead of owning it 2026-05-22 18:40:01 +02:00
proc rtlil: set Module* on inner-process AttrObjects at construction 2026-06-10 14:54:12 +02:00
sat rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
techmap rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
tests Refactored uses of log_id() 2026-05-08 20:59:24 -07:00