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Code Activity
yosys/frontends/verilog
History
Zachary Snow 0f5b646ab8 sv: extended support for integer types 
- Standard data declarations can now use any integer type
- Parameters and localparams can now use any integer type
- Function returns types can now use any integer type
- Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits)
- Added longint type (64 bits)
- Unified parser source for integer type widths
2021-02-28 16:31:56 -05:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
preproc.cc verilog: error on macro invocations with missing argument lists 2021-02-19 09:18:41 -05:00
preproc.h Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
verilog_frontend.cc Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
verilog_frontend.h frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
verilog_lexer.l sv: extended support for integer types 2021-02-28 16:31:56 -05:00
verilog_parser.y sv: extended support for integer types 2021-02-28 16:31:56 -05:00