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24 lines
497 B
Verilog
24 lines
497 B
Verilog
module \$add (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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generate
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if ((A_WIDTH == 32) && (B_WIDTH == 32))
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begin
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wire [15:0] CARRY = |{A[15:0], B[15:0]} && ~|Y[15:0];
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assign Y[15:0] = A[15:0] + B[15:0];
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assign Y[31:16] = A[31:16] + B[31:16] + CARRY;
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end
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else
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wire _TECHMAP_FAIL_ = 1;
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endgenerate
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endmodule
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