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19 lines
271 B
Verilog
19 lines
271 B
Verilog
module test(input CLK, ARST,
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output [7:0] Q1, Q2, Q3);
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wire NO_CLK = 0;
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always @(posedge CLK, posedge ARST)
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if (ARST)
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Q1 <= 42;
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always @(posedge NO_CLK, posedge ARST)
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if (ARST)
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Q2 <= 42;
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else
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Q2 <= 23;
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always @(posedge CLK)
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Q3 <= 42;
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endmodule
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